This invention relates to data transfers between buses using DMA (Direct Memory Access) devices and particularly to the use of modified DMA devices to transfer data across a common bus between two DMA devices.
Direct Memory Access is a data transfer technique for moving data between two devices, commonly a memory and a peripheral device without the intervention of a system processor. Early computer systems had external devices for supplying or receiving data to and from the system memory where all the devices were controlled by the processor. DMA provided a way to access the memory without using processor resources. The DMA would steal a cycle, i.e., interrupt the processor which was held off for a cycle, to perform the memory function. In some cases, the processor would not access the memory for a cycle, e.g., during a register-to-register operation. The DMA could, in response to a processor signal that a nonmemory function was being executed, use the memory during that cycle to read or to write data.
Early DMA operations were performed by the peripheral device but improvements resulted in separate DMA devices that were coupled between a local bus and an external bus. The local bus typically coupled the processor and its memory. The external bus coupled at least one peripheral data device to the DMA device, but the usual case was that several peripheral data devices were coupled to the external bus.
The data devices on the external bus could thereby operate independently from the system processor. In fact, the data device could be another processor with its own memory and local bus. Another such data device might be a printer that needed an occasional transfer of data specifying the print information.
The data devices on the external bus would be coupled to the DMA device which would control both the external and the local bus to transfer data from a data device to the memory or vice versa.
As systems increased in size and complexity, more than one external bus was provided. Another DMA device would be used to couple the second external bus to the local bus.
To transfer data between the external buses, e.g., from a data device on one external bus to a data device on the other external bus, the data is moved from the first external bus into the memory on the local bus by the first DMA device and then moved from the memory to the second external bus by the second DMA device.
Such systems are described in the prior art.
U.S. Pat. No. 4,682,285 shows a unit for coupling a plurality of processing systems with one or more peripheral units using an exchange bus within each processing systems that can be coupled to a local bus through suitable bus controllers. There is no disclosure or suggestion of the ability of the bus controllers to couple the individual exchange buses of the processing systems together via the local bus.
U.S. Pat. No. 4,400,775 discloses local and global memories shared by several arithmetic-control units and the access control.
U.S. Pat. No. 4,773,000 describes a DMA system for reducing processor interrupts by using a dedicated portion of the main memory as a random access buffer, limiting the accessible memory of each DMA device.
U.S. Pat. No. 4,878,166 describes a RISC processor system interconnecting a set of high performance devices on a local bus to a set of low performance devices on a remote bus. The DMA interface between the local and the remote bus facilitates transfers between devices having differing performance characteristics.
U.S. Pat. No. 4,837,677 discloses a bus interconnection control in a microprocessor-based multiport communications adapter. The system transfers data using either DMA or interrupt methods. The DMA/interrupt controller and arbiter governs data transfers among a plurality of ports.
U.S. Pat. No. 4,495,567 shows control of access by several data processors to each of several memories, each processor having a local memory to which access is controlled by a bus controller.
An example of a commercially available direct memory access controller is a Motorola MC6844 device. It can control four separate channels independently from one another and each of the channel controllers is separately programmable.
The transfer of data from a first bus to a memory and then from the memory to a second bus requires two transfer operations. The transfer of data from one external bus to another can be performed in one transfer cycle by coupling the external buses with a separate DMA device. This increases the complexity of the system and the contention problems associated with the DMA devices competing for control of the buses.
The present invention allows transfers from one external bus to the other without utilizing the memory on the local bus and without the addition of another DMA device. The DMA devices transfer data from one DMA device to the other via the connection to the local bus.
In accordance with the invention, first, second, and third buses for carrying data signals are coupled by first and second direct memory access devices so that one of the latter is coupled between the first and the second buses and the other is coupled between the second and the third buses. The direct memory access devices are coupled together to transfer data between them over the second bus so that data can be transferred between said first and third bus means via said second bus means.